• Class homepage: http://www.cs.uiuc.edu/class/sp08/cs533/
• Lecture Notes: http://www.cs.uiuc.edu/class/sp08/cs533/notes.htm
• Reading List: http://www.cs.uiuc.edu/class/sp08/cs533/papers.htm
• CiteULike? Reading List: http://www.citeulike.org/user/rblake/tag/cs533

• Prof: Torrellas

• 2008-04-29: On Apr 29th do last homework

Terms I need to define

• consistency
• coherence
• cache coherence
• false sharing
• trace cache
• bypass logic

2008-03-04

2008-02-28

• managing on chip parallelism - cache coherence, etc.
• off chip memory bandwidth
  • better software
  • optical interconnects to memory
  • hardware tricks, backup cache.
• power - not really a problem. Powerdown cores that aren't in use.
• Using them effectively. - software problem

2008-02-19

• exchange vs test and set: test and set can only set 1.
• test and set consumes bandwidth, so test first to load it into the cache, then do the iterations of reading and writing.
  • all processors invalidate each other over and over with test and set, naively.
  • guard the test and set with an if block, only test and set when var == 0;
• HEP - optimized for producer consumer.

2008-02-14

• prefetching has no effect on the consistency.
• more on prefetching tables in memory controller: ISCA 20005 Wanisch

2008-02-12

• sequential consistency more expensive to implement than release consistency, so release consistency used more ofter
• in practice, everyone uses speculative execution, so SC and RC perform about the same.

Prefetching

2008-02-07

• http://www.cs.uiuc.edu/class/sp08/cs533/reading_list/2b.ps
  • old paper, processors no longer stall on reads
  • gives design methodology

Lock free syncronization has problems on processors with release consistency.